Join Date: Feb ; Posts: 3; Helped: 0 / 0; Points: ; Level: 3 First you create the test bench in the same proyect where you VHDL. I have a testbench but can't figure out how to connect it in Modelsim. When I start RTL Simulation I only get my counter design in Modelsim so there is no testbench. Join Date: Aug ; Location: California; Posts: 4, VHDL Simulation Warning Reported in Main Window. .. Verilog testbench with the VHDL counter or vice versa. Related Reading .. order, and modified date.
You will see the window presented on the left.
Tutorial - Using Modelsim for Simulation, For Beginners
Projects in Modelsim have the file extension. Leave the other settings to their default. This just says that all code will be compiled into the library "work".
Click on Add Existing File as shown in the picture to the right. Keep other settings at their default. Click OK when done. Modelsim Project Window - Files Added to Project Notice now that the files have been added successfully to your project.
See those two blue question marks in the Modelsim Project Window Figure above?
That means that Modelsim has not compiled the files yet. You will need to compile the source files. You should see messages in the Console window appear in green that the compile was successful as shown in the screenshot below.
This opens the Start Simulation Window. The simulation is ready and waiting.
Now, the majority of the time that you use Modelsim will be spent looking at the waveform view. The waveform view contains waves binary 0's and 1's, hexadecimal digits, binary digits, enumerated types, etc for all of the signals in your design.
Tutorial - Using Modelsim for Simulation, for Beginners.
It shows how your module reacts to different stimulus. The next figure shows you what your waveform view looks like, but first you need to add some signals to monitor. In this example, we will monitor all of the signals in the test bench. You can also click and drag signals to the waveform window from other windows in Modelsim. Here is your waveform window.
- Re: testbench simulation
- How to simulate VHDL testbench in Modelsim?
- Getting Started
All of the test bench signals have been added as signals your can monitor. To run the simulation, click the Icon with a little piece of paper and a down arrow next to the ns time. First we will try a random input sequence that also contains the correct sequence embedded inside the random sequence If this is an undesired feature for a lock, you'll have to redesign the system.
Next we will try a partially correct code as an input sequence: To find out what went wrong, we'll have to debug our design. Macro do files are files that contain ModelSim and sometimes Tcl commands to control the simulator and the simulation. Macro files are useful files that can help you to reduce repetitive work like setting up the simulator open debug windows or simulation initialize signals and so on.
You can even use them run the whole simulation with one command.
ModelSim Tutorial: Getting Started
Once you have finished the simulation, create a macro file from the commands you have used and then you can run the same simulation just by calling the macro file. It is very useful, since you always modify your design and you must simulate it again with the same data as before. We will, however, modify the file a bit before we will use it. You might have made, for example, typos when writing some commands and there are also some comments written by ModelSim which will be removed.
So, use your favorite text editor and edit a file named transcript: Your new macro file should look something like this example of lock. You could also divide the macro file in two parts -- startup. Now whenever simulator is invoked in this directory it will execute the startup.
Now you can run the whole simulation we have done so far just by calling your macro file: Note that before an error can be debugged, it must be detected and repeated. In general, one should automate both stimulus generations and response checking. For example, clock signal is usually copied few times. Note that ordering and proper radix have a major impact on readability and hence debuggability. It is recommended that signals activity "flows from top left to bottom right". You may group signals according to their purpose by adding divider texts to the signal list.
Dividers help working with large number of signals.
Note that there is 4 different zooming options: The last one keeps the active cursor in the middle of window which is handy.
When you have selected a signal from wave window, you search for falling and rising edges with these buttons. You may also search for certain value. First letter denotes the radix: The examine command can be used to examine the values of both signals and variables in your code: